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PROTECTION PRODUCTS Description
RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The RClamp series has been specifically designed to protect sensitive components which are connected to data and transmission lines from overvoltage caused by ESD (electrostatic discharge), EFT (electrical fast transients), and lightning. The unique design of the RClamp series devices incorporates four surge rated, low capacitance steering diodes and a TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The internal TVS diode prevents over-voltage on the power line, protecting any downstream components. The RClampTM0504M has a low typical capacitance of 3pF and operates with virtually no insertion loss to 1GHz. This makes the device ideal for protection of highspeed data lines such as USB 2.0, Firewire, and DVI interfaces. The RCLAMP0504M is designed to have ease of layout by allowing the traces to run straight through the device. This ease of layout coupled with the low capacitance and clamping voltage of the RCLAMP0504M makes it the superior choice for protecting four high speed lines. The low capacitance array configuration allows the user to protect four high-speed data or transmission lines. The low inductance construction minimizes voltage overshoot during high current surges. They may be used to meet the ESD immunity requirements of IEC 61000-42, Level 4 (15kV air, 8kV contact discharge).
RailClamp Low Capacitance TVS Diode Array
PRELIMINARY Features
ESD protection for high-speed data lines to IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-5 (Lightning) 12A (8/20s) IEC 61000-4-4 (EFT) 40A (5/50ns) Array of surge rated diodes with internal TVS Diode Small package saves board space Protects four I/O lines and one Vcc line Low capacitance: 3pF typical Low clamping voltage Low operating voltage: 5.0V Solid-state silicon-avalanche technology
RCLAMP0504M
Mechanical Characteristics
JEDEC MSOP 10L package Molding compound flammability rating: UL 94V-0 Marking : Marking code and date code Packaging : Tape and Reel per EIA 481 Lead Finish: Matte Tin
Applications
Digital Video Interface (DVI) 10/100/1000 Ethernet Monitors and Flat Panel Displays Notebook Computers High Definition Multi-Media Interface (HDMI) USB 2.0 Power & Data Line Protection IEEE 1394 Firewire Ports Projection TV
Circuit Diagram
Schematic & PIN Configuration
Pin 3
Line 1 1 NC
Pin 1 Pin 4 Pin 6 Pin 9
NC Line 2 GND NC Line 4
Vcc Line 3 NC
Pin 8
MSOP-10L (Top View)
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RCLAMP0504M
PROTECTION PRODUCTS Absolute Maximum Rating
Rating Peak Pulse Power (tp = 8/20s) Peak Pulse Current (tp = 8/20s) ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) Lead Soldering Temperature Operating Temperature Storage Temperature Symbol Ppp IPP VESD TL TJ TSTG Value 300 12 15 8 260 (10 sec.) -55 to +125 -55 to +150
PRELIMINARY
Units Watts A kV C C C
Electrical Characteristics (T=25oC)
Parameter Reverse Stand-Of f Voltage Reverse Breakdown Voltage Reverse Leakage Current Forward Voltage Clamping Voltage Clamping Voltage Clamping Voltage Junction Capacitance
Symbol VRWM VBR IR VF VC VC VC Cj
Conditions Pin 3 to 8 It = 1mA Pin 3 to 8 VRWM = 5V, T=25C Pin 3 to 8 If = 15mA IPP = 1A, tp = 8/20s Any I/O pin to Ground IPP = 5A, tp = 8/20s Any I/O pin to Ground IPP = 12A, tp = 8/20s Any I/O pin to Ground VR = 0V, f = 1MHz Any I/O pin to Ground VR = 0V, f = 1MHz Between I/O pins
Minimum
Typical
Maximum 5
Units V V
6 5 1.2 1 2 .5 17.5 25 3 1.5 5
A V V V V pF pF
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RCLAMP0504M
PROTECTION PRODUCTS Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
110 100 % of Rated Power or IPP 90 80 70 60 50 40 30 20 10 0
PRELIMINARY
Power Derating Curve
Peak Pulse Power - PPP (kW)
1
0.1
0.01 0.1 1 10 Pulse Duration - tp (s) 100 1000
0
25
50
75
100
125
150
Ambient Temperature - TA (oC)
Pulse Waveform
110 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 Time (s) 20 25 30 td = IPP/2
PP
Clamping Voltage vs. Peak Pulse Current
Waveform Parameters: tr = 8s td = 20s
30.00 Clamping Voltage -Vc (V) 25.00 20.00 15.00 10.00 5.00 0.00 0.00 Waveform Parameters: tr = 8s td = 20s 2.00 4.00 6.00 8.00 10.00 12.00
Percent of I
e-t
Peak Pulse Current - Ipp (A)
Forward Voltage vs. Forward Current
5
Capacitance vs. Reverse Voltage
I/O to GND f = 1MHz 4 Capacitance - Cj (pF)
7.00 Forward Voltage -VF (V) 6.00 5.00 4.00 3.00 2.00 1.00 0.00 0.00 Waveform Parameters: tr = 8s td = 20s
3
2
1
0 0 1 2 3 4
2.00
4.00
6.00
8.00
10.00
12.00
Forward Current - IF (A)
Reverse Voltage - V R (V)
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RCLAMP0504M
PROTECTION PRODUCTS Typical Characteristics (Con't)
Insertion Loss S21
CH1 S21 LOG 3 dB/ REF 0 dB
PRELIMINARY
Analog Cross Talk
CH1 S21 LOG 20 dB/ REF 0 dB
START
.030 000 MHz
STOP 3 000. 000 000 MHz
START
.030 000 MHz
STOP 3 000. 000 000 MHz
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RCLAMP0504M
PROTECTION PRODUCTS Applications Information
Device Connection Options for Protection of Four High-Speed Data Lines The RCLAMP0504M TVS is designed to protect four data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Flow Through Layout The RCLAMP0504M is designed for have ease of PCB layout by allowing the traces to run straight through the device. Figure 1 shows the proper way to design the PCB board trace in order to use the flow through layout for two line pairs. The solid line represents the PCB trace. Note that the PCB traces are used to connect the pin pairs for each line (pin 1 to pin 10, pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6). For example, line 1 enters at pin 1 and exits at Pin 10 and the PCB trace connects pin 1 and 10 together. This is true for lines 2, 3, and 4. The negative reference (Gnd) is connected at pin 8. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference is connected at pin 3. The options for connecting the positive reference are as follows: 1. Figure 2 shows the connection scheme to protect both data lines and the power line by connecting pin 3 directly to the positive supply rail (VCC). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail. 2. In applications where no positive supply reference is available, or complete supply isolation is desired, figure 3 shows how the internal TVS may be used as the reference. In this case, pin 3 is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop). This ease of layout coupled with the low capacitance and clamping voltage of the RCLAMP0504M makes it the superior choice to protect two high speed line pairs.
PRELIMINARY
Figure 1. Flow through Layout for two Line Pairs
Line 1 Line 2 Vcc Line 3 Line 4
1
Line 1 Line 2 Gnd Line 3 Line 4
Figure 2. Data Line and Power Supply Protection Using Vcc as reference
Line 1 Line 2 Vcc Line 3 Line 4
1
Line 1 Line 2 Gnd Line 3 Line 4
Pro Internal TV Figure 3. Data Line Protection Using Internal T V S Diode as Reference
Line 1 Line 2 Gnd Line 3 Line 4
Line 1 Line 2 NC Line 3 Line 4
1
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RCLAMP0504M
PROTECTION PRODUCTS Applications Information (continued)
ESD Protection With RailClamps RailClamps are optimized for ESD protection using the rail-to-rail topology. Along with good board layout, these devices virtually eliminate the disadvantages of using discrete components to implement this topology. ConPIN Descriptions sider the situation shown in Figure 4 where discrete diodes or diode arrays are configured for rail-to-rail protection on a high speed line. During positive duration ESD events, the top diode will be forward biased when the voltage on the protected line exceeds the reference voltage plus the VF drop of the diode. For negative events, the bottom diode will be biased when the voltage exceeds the VF of the diode. At first approximation, the clamping voltage due to the characteristics of the protection diodes is given by: VC = VCC + VF VC = -VF (for positive duration pulses) (for negative duration pulses)
PRELIMINARY
"Rail-T Pro Topology Figure 4 - "Rail-To-Rail" Pro tection Topology (First Approximation)
However, for fast rise time transient events, the effects of parasitic inductance must also be considered as shown in Figure 5. Therefore, the actual clamping voltage seen by the protected circuit will be: VC = VCC + VF + LP diESD/dt (for positive duration pulses) VC = -VF - LG diESD/dt (for negative duration pulses) ESD current reaches a peak amplitude of 30A in 1ns for a level 4 ESD contact discharge per IEC 61000-4-2. Therefore, the voltage overshoot due to 1nH of series inductance is: V = LP diESD/dt = 1X10-9 (30 / 1X10-9) = 30V Example: Consider a VCC = 5V, a typical VF of 30V (at 30A) for the steering diode and a series trace inductance of 10nH. The clamping voltage seen by the protected IC for a positive 8kV (30A) ESD pulse will be: VC = 5V + 30V + (10nH X 30V/nH) = 335V This does not take into account that the ESD current is directed into the supply rail, potentially damaging any components that are attached to that rail. Also note
Figure 5 - The Effects of Parasitic Inductance When Using Discrete Components to Implement Rail-T Pro Rail-To-Rail Pr o t ection
Rail-T Pro Figure 6 - Rail-To-Rail Protection Using RailClamp TV Arrays RailClam p T V S Arrays
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RCLAMP0504M
PROTECTION PRODUCTS Applications Information (continued)
that it is not uncommon for the VF of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. It is also possible that the power dissipation capability of the discrete diode will be exceeded, thus destroying the device. The RailClamp is designed to overcome the inherent disadvantages of using discrete signal diodes for ESD suppression. The RailClamp's integrated TVS diode helps to mitigate the effects of parasitic inductance in the power supply connection. During an ESD event, the current will be directed through the integrated TVS diode to ground. The maximum voltage seen by the protected IC due to this path will be the clamping voltage of the device. Circuit Board Layout Recommendations for Suppression of ESD. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: Place the device near the input terminals or connectors to restrict transient coupling. Minimize the path length between the TVS and the protected line. Minimize all conductive loops including power and ground loops. The ESD transient return path to ground should be kept as short as possible. Never run critical signals near board edges. Use ground planes whenever possible. Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small compared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint.
PRELIMINARY
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RCLAMP0504M
PROTECTION PRODUCTS Applications Information (continued)
DVI Protection The small geometry of a typical digital-visual interface (DVI) graphic chip will make it more susceptible to electrostatic discharges (ESD) and cable discharge events (CDE). Transient protection of a DVI port can be challenging. Digital-visual interfaces can often transmit and receive at a rate equal to or above 1Gbps. The high-speed data transmission requires the protection device to have low capacitance to maintain signal integrity and low clamping voltage to reduce stress on the protected IC. The RCLAMP0504M has a low typical insertion loss of <0.4dB at 1GHz (I/O to ground) to ensure signal integrity and can protect the DVI interface to the 8kV contact and 15kV air ESD per IEC 61000-42 and CDE. Figure 7 shows how to design the RCLAMP0504M into the DVI circuit on a flat panel display and a PC graphic card. The RCLAMP0504M is configured to provide common mode and differential mode protection. The internal TVS of the RCLAMP0504M acts as a 5 volt reference. The power pin of the DVI circuit does not come out through the connector and is not subjected to external ESD pulse; therefore, pin 3 should be left unconnected. Connecting pin 3 to Vcc of the DVI circuit may result in damage to the chip from ESD current.
PRELIMINARY
1
1
1
1
Figure 7 - Digital Video Interface (DVI) Protection
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RCLAMP0504M
PROTECTION PRODUCTS Outline SO-8 Outline Drawing --MSOP 10L
e A N 2X E/2 PIN 1 INDICATOR ccc C 2X N/2 TIPS 12 B E1 E H GAGE PLANE 0.25 (L1) D aaa C SEATING PLANE A2 C A1 bxN bbb C A-B D A DETAIL L c SIDE VIEW SEE DETAIL D
PRELIMINARY
DIM
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.043 .000 .006 .030 .037 .007 .011 .003 .009 .114 .118 .122 .114 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 0 8 .004 .003 .010 1.10 0.00 0.15 0.75 0.95 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0 8 0.10 0.08 0.25
A
01
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA.
Land Pattern - MSOP 10L
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
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RCLAMP0504M
PROTECTION PRODUCTS Marking Codes PRELIMINARY
504M XXXX
* XXXX = Date Code ** Dot indicates Pin 1
Ordering Information
Part Number RClamp 0504M.TBT Lead Finish Matte Sn Qty per Reel 500 Reel Size 7 Inch
Note: Lead finish is lead-free matte tin.
RailClamp and RClamp aremarks of Semtech Corporation.
Contact Information
Semtech Corporation Protection Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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